This shows you the differences between two versions of the page.
Both sides previous revision Previous revision Next revision | Previous revision Next revision Both sides next revision | ||
chumbyhackerboard:vga [2010/09/21 04:10] ladyada |
chumbyhackerboard:vga [2010/09/21 05:28] ladyada |
||
---|---|---|---|
Line 4: | Line 4: | ||
use 278 & 556 ohm resistors for the R2R ladder, this will give you ~0.7v signal when plugged into a 75 ohm termination such as a monitor. | use 278 & 556 ohm resistors for the R2R ladder, this will give you ~0.7v signal when plugged into a 75 ohm termination such as a monitor. | ||
- | ====== VSync ====== | ||
- | We want to get the Vsync to about 60hz | ||
- | By default, the 'internal' LCD sync rate is 117 Hz | + | ====== Horizontal Sync HW_LCDIF_VDCTRL2====== |
- | <code> | + | |
- | chumby-:/ # cat /proc/driver/chumbyfwfb/fb_stats | + | |
- | PXP frequency: 59 Hz | + | |
- | LCDIF frequency: 117 Hz | + | |
- | VSYNC Edge IRQs: 49077 | + | |
- | Cur Frame Done IRQs: 49224 | + | |
- | Missed PXP firings: 5 | + | |
- | </code> | + | |
- | This is set by the HW_CLKCTRL_PIX register | + | For the LCD, this is by default = 0x45000190 |
- | <code> | + | We want... |
- | chumby-:/ # regutil -r HW_CLKCTRL_PIX | + | |
- | Value at 0x80040060: 0x0000001d | + | |
- | </code> | + | |
- | Lets divide the frequency by 2 which means multiplying the divider by two | + | * Per horizontal line: 640 pixels |
+ | * Front porch: 16 pixels | ||
+ | * Sync pulse width: 96 pixels | ||
+ | * Back porch: 48 pixels | ||
- | <code> | + | SO! |
- | chumby-:/ # regutil -w HW_CLKCTRL_PIX=0x38 | + | |
- | Setting 0x80040060: 0x0000000e -> 0x00000038 ok | + | |
- | </code> | + | |
- | <code> | + | HW_LCDIF_VDCTRL2 = (96) << 24 | (640 + 16 + 96+ 48) = 0x60000320 |
- | chumby-:/ # cat /proc/driver/chumbyfwfb/fb_stats | + | |
- | PXP frequency: 32 Hz | + | |
- | LCDIF frequency: 62 Hz | + | |
- | VSYNC Edge IRQs: 69919 | + | |
- | Cur Frame Done IRQs: 70118 | + | |
- | Missed PXP firings: 5 | + | |
- | </code> | + | |
- | Actually, to get the closest to 60 Hz. I went with HW_CLKCTRL_PIX=0x37 (so says the tek 'scope) | + | ====== Vsync HW_LCDIF_VDCTRL1 ====== |
+ | |||
+ | For the LCD, this is by default = 0x0000011a (dec. 282) | ||
+ | |||
+ | We want... | ||
+ | |||
+ | * Per vertical line: 480 horizontal lines | ||
+ | * Front porch: 11 horizontal lines | ||
+ | * Sync pulse: 2 horizontal lines | ||
+ | * back porch: 31 horizontal lines | ||
+ | |||
+ | so HW_LCDIF_VDCTRL1 = 524 (0x20C) | ||
+ | |||
+ | ====== HW_LCDIF_VDCTRL0 ====== | ||
+ | |||
+ | <file> | ||
+ | VSYNC_OEB = 0 (generate vsync) | ||
+ | ENABLE_PRESENT = 0 (no enable necessary) | ||
+ | 0x0 | ||
+ | |||
+ | VSYNC_POL = 0 (negative sync!) | ||
+ | HSYNC_POL = 0 (negative sync!) | ||
+ | DOTCLK_POL = D/C | ||
+ | ENABLE_POL = D/C | ||
+ | 0x0 | ||
+ | |||
+ | VSYNC_PERIOD_UNIT = 1 (count in lines) | ||
+ | VSYNC_PULSE_WIDTH_UNIT = 1 (count in lines) | ||
+ | 0x3 | ||
+ | |||
+ | HALF_LINE = 0 | ||
+ | HALF_LINE_MODE = 1 (no half line for vga, right?) | ||
+ | 0x4 | ||
+ | |||
+ | VSYNC_PULSE_WIDTH = 2 | ||
+ | 0x2 | ||
+ | </file> | ||
+ | |||
+ | -> 0x00340002 | ||
+ | |||
+ | ====== HW_LCDIF_VDCTRL3 ====== | ||
+ | by default = 0x004b0027 | ||
+ | |||
+ | * MUX_SYNC_SIGNALS = 0 | ||
+ | * VSYNC_ONLY = 1 (?) | ||
+ | * HORIZONTAL_WAIT_CNT = 48 (h back porch)= 0x30 | ||
+ | * VERTICAL_WAIT_CNT = 31 (v back porch) = 0x1F | ||
+ | |||
+ | -> 0x0030001F | ||
+ | |||
+ | ====== HW_LCDIF_TRANSFER_COUNT ====== | ||
+ | By default, (32x0x240 LCD) = 0x00f00140 | ||
+ | |||
+ | For 640x480 VGA it should be = 0x01E00280 | ||
+ | |||
+ | ====== HW_CLKCTRL_PIX ====== | ||
+ | |||
+ | So the main clock is 454 right? | ||
+ | |||
+ | To get a pixel clock of 25.175 MHz, 454 MHz / 18 -> DIV = 0x12 | ||
+ | CLKGATE = 0 | ||
+ | DIV = 0x12 -> CLK of 21 Mhz | ||
+ | |||
+ | Hmm, guess our chip isnt running at 454? Or is it our scope? Try 0x0F for 25MHz which matches with eveything else. Which means we're running at 375MHz? | ||
+ | |||
+ | ===== Results? ===== | ||
+ | PIXCLK = 0x0F | ||
+ | |||
+ | HSync = 31.3Khz (should be 31.46) | ||
+ | |||
+ | Vsync = 59.75 Hz (should be 60.04) | ||
+ | |||
+ | Vsync negative pulse = 63.9 uS (should be 63.57) (it is low from the negative edge of one HSync to another negative Hsync edge) | ||
+ | |||
+ | Hsync negative pulse = 3.83 uS (should be 3.81) |